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IBM Previews the POWER6


At the MicroProcessor Forum, Dr. Brad McCredie of IBM continued to tease out particulars regarding the POWER6. The presentation discussed a lot of general microarchitecture features, but did not reveal many specific details; a full revelation of the microarchitecture will likely have to wait till ISSCC, next February. However, from the details that were revealed, it is clear that the POWER6 inherited many characteristics from its predecessors, yet made substantial improvements in others.

The POWER6 is targeted to run at 4-5GHz and was fabricated on IBM’s 65nm SOI process with 10 layers of metal. Compared to the 90nm process, there is a 30% performance increase at a given power level, largely due to the use of dual-stress line technology. IBM’s 65nm process offers a 0.65um high performance SRAM cell, and a 0.45um cell for density. The array cells use a lower supply voltage compared to the logic, to reduce power consumption. By all accounts, IBM heavily emphasized circuit design in the POWER6, as the means to increase frequency, while prior designs relied extensively on automated tools and logic design. This helps to explain how IBM was able to dramatically increase the frequency, but it is still hard to believe that such optimizations were never made previously. Leaving a 2x performance boost on the table seems unconscionable from a competitive positioning point of view.

Like the previous two generations, the POWER6 focuses on a big system environment where system architecture makes a substantial difference. Each POWER6 MPU is implemented as a two way CMP design, integrating two simultaneous multithreaded processors along with private per-core L2 caches in a 340mm2 die. For high-end models, four POWER6 MPUs will be packaged in a single multi-chip module, along with four L3 victim caches, each 32MB. Figure 1 below shows a high level comparison of the POWER5+ and POWER6 MPUs.




IBM’s POWER6 based systems are aiming for general availability in mid 2007, somewhat later than previous roadmaps and public statements indicated. This would put the POWER6 initially up against Intel’s Montvale, and the joint Sun and Fujitsu APL, presumably based on the SPARC64-VI. On the x86 side, the contemporaries would be Intel’s Tigerton, and AMD’s Rev. H, both quad core designs.

IBM is claiming a factor of two performance increase, which would be consistent with the vastly higher clockspeeds and increases in raw system bandwidth. Assuming proper execution on IBM’s behalf, they will have a very strong competitive position come next year. The only real challenges to IBM’s current performance leadership would come in 2008, when both Sun’s massively multithreaded Rock and Intel’s long awaited Tukwila arrive. IBM’s roadmaps currently include the POWER6+, which is presumably a 45nm derivative product. Judging by past practices, the POWER6+ will debut in the second half of 2008, probably just in time to dash the hopes of rivals.

One thing is clear though; IBM has found a lever that they can use to defer the inexorable growth of x86 MPUs; exotic packaging and system bandwidth. It is readily apparent that commodity devices cannot afford such extravagances, and cannot match the impressive system architecture that IBM’s strategy hinges on.

Read the entire article, here.


Published Friday, October 20, 2006 6:55 AM by David Marshall
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