Quoting EE Times Asia

Freescale is now sampling the first dual-core versions of its PowerQuicc processors, aimed at telecom OEMs. The chips are part of a family that will eventually scale to 32-core devices, said Dan Cronin, VP of R&D for Freescale's networking division.

The processors will use a new on-chip interconnect fabric. They will also embed in hardware a hypervisor, a kind of low-level scheduling unit, co-developed with IBM according to specs set in the Power.org group. Freescale will release an open source reference design for companies that want to build virtualization software that taps into the hypervisor, Cronin said.

"Several other processor companies are doing similar things" with embedded hypervisors, raising the issue of non-standard approaches to virtualization, said Marcus Levy, president of the Multicore Association and host of the expo.

Intel described several extensions it sees on the horizon for its multicore chips, including new on-chip fabrics, scratchpad memories and use of spare cores and schedulers. "Beyond adding to the sheer number of cores, there are several system-level challenges that need to be overcome to tap into the true power of multicore processors," said Pranav Mehta, chief technologist of Intel's embedded group.

Asked how many engineers Intel has working on multicore programming issues, Mehta said, "If I had to guess, I would say it is at least in four digits, but even Intel doesn't think we can solve all the problems here alone."

A handful of chip startups, including Ambric and Intellasys, came to the expo touting novel multicore architectures and proprietary tools to write software for them. One of the newer companies among them, Plurality Ltd, said it will release a 256-core product early next year and simulation models and tools for using it in the next few months.

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