Cadence
Design Systems, Inc. today announced the availability of
the industry's first Verification IP (VIP) in support of the new NVM
Express 1.4 (NVMe) protocol. The Cadence VIP
for NVMe 1.4 enables designers to quickly and thoroughly verify their
storage, data center and high-performance computing (HPC) system-on-chip
(SoC) designs with less effort and a greater assurance that the SoC
will meet the protocol standards.
The Cadence VIP for NVMe 1.4 supports the company's Intelligent System Design strategy,
enabling SoC design excellence through best-in-class IP. For more
information on the Cadence VIP for NVMe 1.4, please visit www.cadence.com/go/NVMeVIP.
The
new Cadence VIP for NVMe 1.4 provides customers with a comprehensive
verification solution to develop high-quality NVMe host and device
controllers quickly, helping reduce overall time to market. The NVMe 1.4
VIP supports built-in integration with the Cadence VIP for PCI Express (PCIe)
5.0 and includes a complete UVM SystemVerilog API for fast integration
and SoC-level test creation. Built with Cadence TripleCheck technology,
customers have access to a verification plan with measurable objectives
linked to the specification features and a comprehensive test suite
with ready-to-run tests to ensure support for the specification.
"The
design team in our company has successfully used the Cadence VIP for
NVMe while developing our products for the flash memory controller,"
said Mr. Takehiko Tsuchiya, Group Manager, Design Technology Group,
Design Technology Innovation Division at KIOXIA Corporation. "The NVMe
1.4 VIP is important for the development of the next generation of our
products, supporting the need for a high-performance data interface."
"The
new NVMe 1.4 specification is designed to address the growing needs of
enterprise systems that utilize PCIe-based solid-state storage," said
Moshik Rubin, Verification IP Product Management Group Director, System
and Verification Group at Cadence. "Cadence is fully dedicated to
supporting the latest standard to ensure customers have the tools they
need to create differentiated end products. Our release of the
first-to-market VIP for NVMe 1.4 is enabling early adopters of the
protocol to reduce risk and ensure their designs comply with the
specification while achieving the fastest path to IP and SoC
verification closure."
The Cadence VIP for NVMe 1.4 with TripleCheck technology is part of the Cadence Verification Suite and is optimized for Xcelium Parallel
Logic Simulation, along with supported third-party simulators. The
Verification Suite is comprised of best-in-class core engines,
verification fabric technologies that support the Cadence Intelligent
System Design strategy, enabling SoC design excellence.