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Phison Electronics 2022 Predictions: PCIe Gen5 SSDs change everything

vmblog predictions 2022 

Industry executives and experts share their predictions for 2022.  Read them in this 14th annual VMblog.com series exclusive.

PCIe Gen5 SSDs change everything

By Sebastien Jean, CTO, Phison Electronics

Imagine if your PC or your phone had 1TB of memory instead of 8-12GB? What if that memory was free and didn't increase the cost of your device? What would it be like to have all your apps load faster than you can swipe? What would games look like with super massive textures? What about augmented reality? Now think about servers. What if your server could hold a 1 PB file in L4 cache? What kind of post processing, machine learning or data mining would be possible?

For the first time, storage can now run at DRAM speed thanks to PCIe Gen5. The SSD cannot replace DRAM, because a CPU is optimized for low latency, low queue depth, 64-bit IO. This is where DRAM excels. The Gen5 SSD is optimized for bulk 4K (4096-bits) IO which fits nicely into the CPU cache model. Today the CPU Level-3 cache size ranges from 10-64MB. The SSD can add GB, TB or even PB as a Level-4 cache. Expect to see the design of games, operating systems and applications change to take advantage of this capability.

1.  The role of SLC SSD will grow

Gaming laptops, 2-in-1 workstations and even education systems all push their DRAM limits in different ways. They can benefit from seamless swapping that is enabled by Gen5 + SLC. Dedicating a portion of the NAND as an SLC namespace allows a single drive to provide low latency high endurance partition while keeping cost low. Expect to see this as a breakout feature in the next 2-3 years.

Creative applications, including video editing, special effects, rendering, modeling, and crypto currency all work on large datasets and run substantially faster with Gen5 SSD. This higher productivity will put more write stress on the SSD, causing them to burn out faster. Trading off 1/3rd the capacity of TLC for 20x higher endurance of SLC is justifiable for these write-intensive applications.

The Level-4 caching role will create a demand for optimized SLC Flash such as Kioxia XL Flash. It provides even lower latency on 4K IO than regular NAND and provides even better endurance for random write workloads. Though today's die densities are too low, a Gen5 Level-4 cache workload will create a demand for this capability that will surely push NAND vendors to explore this new use-case.

2.  SSD and GPU will bypass CPU

Traditionally, applications have kept their active dataset in DRAM because storage was so slow. The arrival of Gen5 SSDs operating at DRAM speeds changes that. Many advanced applications can benefit from direct GPU to SSD communication. Having the CPU act as a middle manager to move the data between both parties is needlessly limiting. In this new model, the CPU makes the decisions in a partnership with the user. Then the GPU pulls the data it needs by working directly with the SSD. Expect to see this new IO flow show up in animation, special effects, crypto currency, CAD, medical modeling, AI and even gaming. Though gaming seems to be a dissonant addition to the list, it also generates a huge real-time data processing problem for the GPU.

3.  SSD will exceed DRAM speed

I've pointed out that Gen5 matters because it allows an SSD to operate at DRAM speeds. Today we are at the low-end of DDR4 equivalent speeds and DRAM has already moved on to DDR5. We will likely see SSD speeds increase faster than DRAM as we move through Gen6 and Gen7. This is because doubling the speed of a physical interface is easier than developing the material science needed for a new silicon process node that enables faster DRAM transistors.

To make DRAM faster, we need to increase the clock frequency. Each process node has a natural inflection point after which any additional frequency increase is inefficient. Power consumption moves from linear growth (which is ok) to a logarithmic (which is super bad). In practical terms, this hockey stick curve means that it is simply not feasible to run a transistor faster past a certain point. Transitioning to a smaller process node moves the inflection point further out which allows next generation transistors to increase their speed.

In contrast to DRAM, an SSD can always run faster on the current process node by increasing the amount of internal parallelism and back-end channels. Unlike DRAM, this kind of doubling scales roughly linearly to the bandwidth increase because the only part of the SSD that runs at the new faster speed is the physical PCIe interface.

Both SSD and DRAM use parallelism, bus-width, voltage scaling and process node reduction to run faster, but DRAM is more dependent on process node than an SSD. Also, SSDs are usually one or two generations behind the cutting-edge process, which means there is a lot of headroom for an instant jump if the additional cost can be justified.

CONCLUSION

The arrival of Gen5 SSD will affect all aspects of computers from CPU design, device architecture and application design.  On consumer devices, the user experience will continue to deepen, pop, and enable super-fast device-side processing.  Edge devices on 5G networks will benefit from doing more with less storage.  Datacenters and enterprises will be able to generate more value though accelerated machine learning, modeling, and inference.  The above predictions are within reach using technologies that are based on things we already know how to do. They just needed storage to catch up to DRAM speed. 

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ABOUT THE AUTHOR

Sebastien Jean 

Sebastien Jean is CTO of Phison Electronics. He is an accomplished leader for large-scale technology solutions in a multi-billion-dollar global market.  His responsibilities include aligning technology with business objectives, engaging customers, generating new business opportunities and building strategic partnerships. Sebastien is recognized for his outstanding analytical, strategic and problem-solving skills, coupled with his ability to communicate the vision to multinational teams.

Published Wednesday, October 20, 2021 7:31 AM by David Marshall
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