ChipAgents announced that eMemory, a leading pure-play developer and provider of logic-based non-volatile memory (Logic NVM), founded in 2000, has deployed ChipAgents to automate critical portions of its functional-model verification workflow for NVM IP.
Using ChipAgents, eMemory reduced the engineering effort for datasheet analysis and verification-testbench construction, the two most labor-intensive stages of its functional-model verification flow, by approximately 80%, from an estimated four days to five hours. The agentic AI workflow also increased verification test patterns by 18% and improved functional coverage by 5%.
The deployment addresses a growing semiconductor engineering challenge: scaling the volume and complexity of IP development without proportionally increasing engineering resources. eMemory delivers more than 40 IP products each month with a small, dedicated functional-model verification team. The traditional process required engineers to manually interpret datasheets, identify inconsistencies, and build verification testbenches, work that was time-consuming, difficult to reuse and vulnerable to human error and implementation bias.
“Semiconductor companies are being asked to develop more products and more complex designs without a corresponding increase in engineering resources,” said William Wang, Founder and CEO of ChipAgents. “eMemory demonstrates what becomes possible when AI agents move beyond code generation and deliver full-flow engineering outcomes. By automating the path from datasheet analysis through testbench generation, ChipAgents helped eMemory dramatically reduce manual engineering effort while expanding verification coverage.”
eMemory deployed a ChipAgents-based agentic AI workflow on NeoFuse, its production one-time-programmable (OTP) NVM IP. The workflow automates three stages of functional-model verification: Datasheet Recognition, which extracts structured information from datasheets; Datasheet Quality, which identifies inconsistencies and documentation errors; and Testbench Generation, which automatically generates verification plans and UVM testbenches. Machine-readable rule decks guide agent actions throughout the process to help ensure consistent and repeatable results.
In testing, ChipAgents processed 10 NeoFuse datasheets in eMemory’s internal datasheet format, containing 120 tables, figures and timing diagrams, and recorded zero mismatches when comparing extracted information with eMemory’s internal specification database. The system also detected all 15 intentionally introduced datasheet errors, including parameter inconsistencies, spelling errors, and missing descriptions, with zero false positives.
ChipAgents then used the datasheet information to automatically generate a functional-model verification plan and UVM testbench. The generated verification environment identified additional scenarios that had not previously been considered, increasing test patterns by 18%.
“ChipAgents has gone beyond serving as an AI evaluator for eMemory’s behavioral model,” said Max Yeh, CAD Director at eMemory. “It has also enabled our engineers to significantly enhance the quality and reliability of our IP datasheets.” To the eMemory team, verification efficiency and consistency are critical to keeping pace with customer requirements. ChipAgents’ AI-native workflow gives eMemory engineers a more repeatable way to turn complex datasheets into verification assets, helping maintain quality at scale while allowing the team to focus its expertise where it adds the most value.
Beyond the controlled NeoFuse evaluation, eMemory deployed ChipAgents’ Datasheet Quality workflow across 100 manually edited production datasheets. The system identified five documentation issues, primarily spelling and unit-notation inconsistencies, demonstrating how agentic AI can help engineering teams surface such issues before they propagate further into the development process.
The eMemory deployment points to an industry-wide shift in semiconductor engineering: agentic AI is moving beyond code generation to orchestrating complex, cross-domain workflows end to end. These workflows often require multiple engineers to interpret technical documentation, apply specialized design rules, and translate specifications into verification-ready assets. By automating more of this reasoning and execution with AI, engineering teams can shorten design cycles, improve verification consistency, and free engineers to focus on the highest-value decisions required to bring increasingly complex chips to market.
