Industry executives and experts share their predictions for 2026. Read them in this 18th annual VMblog.com series exclusive.
By Gaurav Shah, Vice President of Business Development & Strategy, NeuReality
AI infrastructure isn’t scaling – it’s stalling. Model sizes are exploding and GPUs are faster than ever, yet performance is increasingly capped by a familiar failure: data can’t move fast enough to feed compute. The industry keeps adding accelerators, but idle GPUs have become the norm. A widening gap now separates theoretical AI capability and what production systems actually deliver.
In 2026, this approach will break. Networks, memory access, and orchestration, not silicon, will determine what AI systems deliver at scale. Competitive advantage will shift from deploying the most compute to designing the most efficient, resilient, and scalable systems. Winners won’t be those with the biggest models, but those that rebuild compute from the network outward.
Four critical shifts are already underway. Over the next year, they will decisively separate organizations that scale intelligence from those that simply scale cost.
1. Rack-scale networking is the next frontier in AI Infrastructure – the strategic differentiator in the age of trillion-parameter AI
Rack-scale GPU interconnects become mandatory as trillion-parameter models and real-time inference demand tightly coupled, low-latency domains that traditional node-level fabrics cannot deliver. As scale-up systems hit physical limits on bandwidth, power, and packaging, network topology becomes a frontline competitive advantage rather than a backend detail.
AI performance is increasingly defined at the rack level, not at the level of individual servers or nodes. Rack-scale GPU interconnects collapse groups of accelerators into tightly coupled AI supernodes, enabling rapid exchange of parameters, activations, and gradients at speeds traditional PCIe or network hops cannot sustain. Scale-out networking takes center stage, as AI-optimized topologies enable massive distributed clusters, while eliminating fabric-level bottlenecks that would otherwise waste GPU cycles at scale.
Expect fewer, more powerful racks delivering outsized performance, alongside a widening divide between platforms designed around rack-level interconnects and those attempting to stretch legacy architectures beyond their limits. Interconnects move from optional acceleration to core infrastructure, shaping utilization, power efficiency, and overall system economics.
Success depends on eliminating cross-rack bottlenecks. AI-optimized fabrics, topology-aware routing, and intelligent workload placement are essential to maintaining performance as clusters grow. When these elements align, scale-out delivers near-linear gains. When they don’t, systems stall under their own traffic.
Organizations that rethink AI from the network outward will unlock sustained performance and efficiency. Those that don’t will scale cost, complexity, and disappointment. In the AI era, compute alone doesn’t win; architecture does.
2. UEC becomes the hyperscale AI fabric standard
Ethernet for AI is shifting from RoCE-centric “lossless” designs toward Ultra Ethernet Consortium (UEC) transports that assume loss, tolerate reordering, and incorporate richer congestion signaling and multipath routing. This shift delivers the robustness that hyperscale deployments demand.
As AI clusters grow larger and more heterogeneous, RoCE’s dependence on lossless tuning, tight congestion control, and strict flow ordering becomes increasingly fragile. At hyperscale, even small packet loss or microbursts can cascade into meaningful performance degradation and operational complexity.
UEC signals a turning point. UEC-based Ethernet introduces native mechanisms for reliability, congestion resilience, and tolerance for out-of-order delivery, capabilities that align far better with the realities of large AI deployments. This evolution allows Ethernet to support both ends of the AI spectrum: tightly synchronized training clusters and highly dynamic, globally distributed inference fabrics.
Expect gradual but decisive convergence toward UEC-based designs. Hyperscalers will deploy distinct fabric profiles optimized for training determinism and inference elasticity while reducing the operational burden that has plagued RoCE-based environments. Ethernet isn’t disappearing; it’s becoming purpose-built for AI.
3. AI networking demand accelerates with rising NIC-to-CPU ratios
The rapid expansion of AI workloads is driving a structural increase in NIC-to-GPU ratios, reinforcing networking as a critical growth vector within AI infrastructure. Fortune Business Insights projects the global data center networking market will grow from $39.5 billion in 2025 to $93.4 billion by 2032, implying a 13.1% CAGR, driven largely by cloud, AI, and high-performance workloads.? This networking spend is rising alongside overall data center CapEx, with interconnects maintaining a growing share of total infrastructure value as the installed base of GPUs and XPUs exceeds 25 million by 2030.
Most hyperscale AI systems now feature 1:1 NIC-to-GPU configurations – such as NVIDIA’s DGX H100 class systems – with emerging architectures adopting dual-NIC designs per GPU.
This shift is translating directly into upward revisions of vendor forecasts: Cisco reported over $2 billion in AI infrastructure orders in FY2025 and guided for approximately $3 billion in FY2026, while NVIDIA‘s Networking division posted a record $7.3 billion in Q2 FY2025 revenue, nearly doubling year-over-year.
As clusters breach 100,000 servers, scale-out networking has become non-negotiable and a primary driver of vendor differentiation.
4. From proprietary to open: The new era of AI interconnects
The ecosystem is converging around open, high-performance interconnect standards to support large-scale AI clusters, as AI operators recognize that proprietary, siloed fabrics will not scale economically to multi-rack and multi-pod clusters.
Initiatives like UEC and emerging specifications like Ultra Accelerator Link (UALink) and Scale-Up Ethernet/Ethernet for Scale-Up Networking (SUE/ESUN) reflect broad industry recognition that next-gen AI workloads require standardized, low-latency, scale-out and scale-up communication standards.
UEC is defining an Ethernet-based, full-stack architecture with microsecond-level congestion control, link-layer retry, and RDMA-style transports to support scale-out AI and HPC networks spanning tens or hundreds of thousands of accelerators.
In parallel, UALink is introducing an open, low-latency accelerator fabric that can connect up to 1,024 GPUs or XPUs per pod at up to 200 Gbps per lane, positioning itself as a multivendor alternative to proprietary GPU interconnects for scale-up domains.
Complementing these efforts, emerging Ethernet-for-scale-up initiatives like SUE/ESUN focus on standardizing ultra-low-latency, largely lossless single-hop and short-reach links within servers and racks. Aligned with UEC and IEEE 802.3, these standards aim to deliver interoperable, end-to-end open fabrics for next-generation AI clusters.
In addition to these industry driven standards, there is a clear need for creating partnerships that center on the consortia, hyperscalers, and silicon/network vendors that will anchor interoperability, compliance, and performance at scale.
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ABOUT THE AUTHOR
Gaurav Shah is Vice President of Business Development and Strategy at NeuReality, where he leads customer efforts to revolutionize AI inference and accelerate its adoption across sectors including fintech, healthtech, and government. Gaurav has three decades of tech industry experience, working in product marketing and management roles at NVIDIA, Marvell, Tenstorrent, and GlobalFoundries. He is based in the San Francisco Bay area.
